Field effect transistors (FET) have become the dominant active device for very large scale integration (VLSI) and ultralarge scale integration (ULSI) applications, such as logic devices, memory devices and microprocessors, because the integrated circuit FET is by nature a high impedance, high density, low power device. Much research and development activity has focused on improving the speed and integration density of FETs, and on lowering the power consumption thereof.
Integrated circuit FETs are typically fabricated with a gate of polycrystalline silicon (also referred to as polysilicon). In some transistors, the polycrystalline silicon gate is counterdoped, i.e. doped of opposite conductivity from the source and drain regions of the FET. For example, U.S. Pat. Nos. 4,984,043 and 4,990,974, both by coinventor Albert W. Vinal and assigned to the assignee of the present application and both entitled Fermi Threshold Field Effect Transistor, the disclosures of which are hereby incorporated herein by reference, describe a field effect transistor which operates in the enhancement mode without requiring inversion by setting a device's threshold voltage to twice the Fermi potential of the semiconductor material. A polycrystalline silicon gate of opposite conductivity from the source and drain regions is preferably provided, in order to generate a gate contact potential which is equal and opposite to that of the substrate contact potential, thereby neutralizing the effect of the contact potentials. A Fermi threshold field effect transistor which includes a Fermi-Tub region surrounding the source and drain regions is described in U.S. Pat. No. 5,194,923 by coinventor Albert W. Vinal entitled Fermi Threshold Field Effect Transistor With Reduced Gate and Diffusion Capacitance, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated herein by reference. Again, a polycrystalline silicon gate of opposite conductivity type from the source and drain regions is preferably provided.
A major problem in fabricating integrated circuit field effect transistors is masking the top of the polycrystalline silicon gate during source and drain implantation. It is difficult to form a mask on the gate without also masking the substrate face where the source and drain regions are to be implanted. Thus, complicated fabrication techniques have been devised for fabricating a gate cap to be used as a mask during source and drain implantations. Alternatively, counterdoped implants are required in the polycrystalline silicon gate, to counteract the effect of the doping ions accumulated therein as a result of source-drain implant.
Another problem in polycrystalline silicon gate field effect transistors is the contact between the polycrystalline silicon gate and the metal gate electrode thereon. It is desirable to have a low resistance ohmic contact between the metal gate electrode and the polycrystalline silicon gate. The contact should not behave as a Schottky barrier. Absent such a low resistance ohmic contact, device performance suffers.